A tiny gate. A different result.: sources & model

Inspect a connected CMOS cutaway, build a channel, find a circuit’s operating point and follow the charge and energy behind a changing bit.

What supports the explanation?

What this model assumes

1. Fictional classic planar bulk-silicon n-well CMOS, not a current commercial process, microscopy image or manufacturer CAD. Layers are enlarged; overlying dielectric/passivation is omitted for inspection.
2. Fixed 5 V supply, 1 V threshold magnitude, constant mobility, α=1 and λ=0. Body tied to source is a separate assumption from α=1. No subthreshold/gate leakage, channel-length modulation, body effect, velocity saturation, temperature dependence, DIBL, breakdown or junction conduction.
3. Only positive source-referenced device biases and inverter outputs on the stated rails are modeled. No reverse-bias/body-diode or arbitrary terminal-excursion model.
4. Channel shading is a normalized sheet-charge proxy, not counted electrons, carriers per area or a measured flow speed. The limiting saturation profile does not resolve the drain-end high-field region.
5. The 50 ns output-capacitor record omits input-driver energy and gate-network capacitances. The separate lumped gate RC comparison must not be added silently to that ledger. Large loads may not settle before the record ends.
6. The ideal DC balance interval does not predict a real metastability lifetime or reliable analog memory. Source reading and independent numerical checks do not replace a validated compact device model.
7. NIST’s unchanged illustration concerns defect trapping/noise, which is omitted here. The 2N7002 trench-device datasheet is a conditions-reading comparison, not a fitted parameter source.
8. Paper cards encode quantities and topology. No powered device, heating, soldering or physical semiconductor measurement is required. Subject review, learner trials and device/export checks remain release gates.
9. Doping is not bulk net charge: p-type and n-type identify semiconductor doping and majority-carrier roles. The bulk is approximately neutral. A p-type block is not simply a positively charged solid.
10. The chosen gate stack: This classic planar drawing uses a conducting doped-polysilicon gate separated from silicon by a silicon-dioxide dielectric. Layer thickness, inversion shading and contact sizes are enlarged teaching choices, not a fabrication-node model.
11. Four terminals and voltage differences: nMOS uses gate, source, drain and body terminals. In the selected model body is tied to source. VGS and VDS matter: translating all terminals by the same voltage preserves current. Changing source alone changes those differences.
12. A bounded square-law model: Let u=VGS−VT. Current is zero for u≤0; β(uVDS−VDS²/2) for 0≤VDS<u; and βu²/2 for VDS≥u. The teaching values are VT=1 V and βn=1 mA/V². β includes mobility, oxide capacitance per area and a geometry ratio; no physical width or length is inferred.
13. Pinch-off is not an open circuit: The ideal saturation branch has finite current independent of further VDS. It is not cutoff and not a perfect low-resistance closed switch. Extra drain voltage and the high-field drain-end region are outside the displayed limiting channel profile.
14. A charge proxy with a common reference: The channel profile follows the same gradual-channel model. Its plotted magnitude divides the local sheet-charge factor by a fixed 4 V reference, so changing overdrive does not get hidden by renormalizing each curve to itself. Cox is unspecified, so carriers per area are not reported.
15. Conventional current and carriers: nMOS conventional current goes drain to source; electron drift has the opposite direction. pMOS conventional current goes source to drain. The drawn arrows identify direction, not individual trajectories or measured carrier speed.
16. Load-line constraint: With a positive resistor to VDD, solve ID(Vin,Vout)=(VDD−Vout)/R. Vout is a result, not a second independent supply setting. Supply power equals resistor heat plus channel heat in the DC account.
17. Complementary source references: For pMOS use VSG=5−Vin and VSD=5−Vout with positive current magnitude from supply to output. Passing a negative gate-source voltage into the nMOS cutoff formula would wrongly turn this device off.
18. Matched strength, not identical mobility: βp/βn controls abstract relative drive strength. Equal β does not imply equal electron/hole mobility or equal geometry. Moving this parameter does not establish a new measured carrier density.
19. The DC solution can be a set: For matched strengths at Vin=2.5 V, any Vout in [1.5,3.5] V balances the ideal branch currents at 1.125 mA each. With strength ratio b, the balance input is [4√b+1]/[1+√b] and the interval is [VM−1,VM+1]. A solver selecting one point does not make it a unique prediction.
20. Output charge and power: For the lumped load, CL dVout/dt=Ip−In and EC=CL Vout²/2. Instantaneous VDD Ip equals nMOS heat power plus pMOS heat power plus dEC/dt. Zero net capacitor current can coexist with nonzero through-current and heat.
21. An explicit transient record: The model solves one input step, linear ramp or exact-balance hold over 50 ns. It integrates output voltage, both heats, supply energy and supplied charge. Waveform corners are respected, rail violations are reported rather than concealed, and inspecting a time reads the same solved experiment.
22. Delay needs a reference event: Output 50% elapsed time is measured from the start of the input edge. Propagation delay here subtracts the input’s own 50% time. For a finite ramp these numbers differ. If a record does not reach the threshold, no crossing time is invented.
23. Changing capacitance starts a new experiment: At the same voltage, a new capacitance changes stored charge and energy. Therefore changing CL resets the transient and its ledger. For matched abrupt steps, doubling CL doubles this model’s delay and completed cycle energy.
24. A completed ideal cycle: Charging a 10 pF output from 0 to 5 V draws 250 pJ, stores 125 pJ and dissipates 125 pJ in pMOS. Discharge dissipates the stored energy in nMOS. At one million complete charge/discharge cycles per second this contribution is 0.25 mW; it is not total chip power.
25. Gate charging has its own ledger: A separate ideal 10 kΩ–100 pF gate RC example has a 1 μs time constant. Gate-wire current charges an insulated electrode, while ideal DC oxide conduction is absent. Input-driver energy and gate-network capacitances are not included in the output-node experiment.
26. Read the complete specification: Threshold identifies a test current and bias. It does not promise the on-resistance measured at a different gate voltage and current. Ciss is bias-dependent measured input capacitance, not a universal output load. Real leakage also differs from the model’s ideal zero endpoint currents.

What has been checked

Analytical reference cases, conservation or transition invariants, finite drawing commands, bounded setup parsing, discovery and route integrity are checked automatically. These checks do not establish anatomical fidelity, learner outcomes or browser/device compatibility. Independent subject review, learner trials, comprehensive accessibility review and browser video encoding checks remain pending.

Each source supports the associated claim. Sources do not certify this implementation or its visuals.

About the cover illustration

Original offline rendering of the lesson’s classic planar n-well CMOS geometry. Doping colors, enlarged layers and external lumped load are teaching choices, not microscopy, manufacturer CAD or measured process dimensions. The NIST defect-trapping source illustration is separately credited inside the lesson.