Inspect a connected CMOS cutaway, build a channel, find a circuit’s operating point and follow the charge and energy behind a changing bit.
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A gate voltage changes a semiconductor channel. The circuit still needs a source of energy, a voltage difference and time to move charge. Keeping those roles separate explains how a physical device becomes part of a digital decision.
At exact matched balance, Ip=In=1.125 mA. What happens to a capacitor already inside the DC interval?
Net capacitor current is Ip−In=0, but the 5 V supply still delivers 5.625 mW through the branches.
The conducting gate sits above a dielectric. Changing gate bias changes local electrostatics and the inversion layer near the semiconductor surface. It does not mechanically open a trench or feed the output current through the oxide.
This original classic planar model shows n+ source/drain in a p-type body, and p+ source/drain in an n-well. A separate body tap connects nMOS bulk to ground, while the n-well tap connects pMOS body to the supply.
At VGS=3 V, the model supports an inversion channel. Set VDS=0: net DC current is zero. Increase VDS and the current changes, even though the gate setting stayed the same.
In a resistor circuit, transistor current must match resistor current. The output is the intersection of their constraints. Moving an arbitrary marker shows a mismatch rather than creating a new valid DC solution.
With a low input, pMOS supports charging the output from the positive supply. With a high input, nMOS supports discharge to ground. The two drains share the output, while both insulated gates share the input.
At one exact input, the ideal flat saturation laws admit a range of DC outputs. Equal branch currents can produce zero net charging while still drawing supply current and producing heat.
A prescribed input step can happen instantly in this model, but the finite output capacitance preserves output-voltage continuity. Current changes its charge over time. A bigger load requires a new initial energy account.
The linked named-device datasheet has different device structure and test conditions. It helps teach careful reading; it does not calibrate this fictional planar CMOS model.
p-type and n-type identify semiconductor doping and majority-carrier roles. The bulk is approximately neutral. A p-type block is not simply a positively charged solid.
This classic planar drawing uses a conducting doped-polysilicon gate separated from silicon by a silicon-dioxide dielectric. Layer thickness, inversion shading and contact sizes are enlarged teaching choices, not a fabrication-node model.
nMOS uses gate, source, drain and body terminals. In the selected model body is tied to source. VGS and VDS matter: translating all terminals by the same voltage preserves current. Changing source alone changes those differences.
Let u=VGS−VT. Current is zero for u≤0; β(uVDS−VDS²/2) for 0≤VDS<u; and βu²/2 for VDS≥u. The teaching values are VT=1 V and βn=1 mA/V². β includes mobility, oxide capacitance per area and a geometry ratio; no physical width or length is inferred.
The ideal saturation branch has finite current independent of further VDS. It is not cutoff and not a perfect low-resistance closed switch. Extra drain voltage and the high-field drain-end region are outside the displayed limiting channel profile.
The channel profile follows the same gradual-channel model. Its plotted magnitude divides the local sheet-charge factor by a fixed 4 V reference, so changing overdrive does not get hidden by renormalizing each curve to itself. Cox is unspecified, so carriers per area are not reported.
nMOS conventional current goes drain to source; electron drift has the opposite direction. pMOS conventional current goes source to drain. The drawn arrows identify direction, not individual trajectories or measured carrier speed.
With a positive resistor to VDD, solve ID(Vin,Vout)=(VDD−Vout)/R. Vout is a result, not a second independent supply setting. Supply power equals resistor heat plus channel heat in the DC account.
For pMOS use VSG=5−Vin and VSD=5−Vout with positive current magnitude from supply to output. Passing a negative gate-source voltage into the nMOS cutoff formula would wrongly turn this device off.
βp/βn controls abstract relative drive strength. Equal β does not imply equal electron/hole mobility or equal geometry. Moving this parameter does not establish a new measured carrier density.
For matched strengths at Vin=2.5 V, any Vout in [1.5,3.5] V balances the ideal branch currents at 1.125 mA each. With strength ratio b, the balance input is [4√b+1]/[1+√b] and the interval is [VM−1,VM+1]. A solver selecting one point does not make it a unique prediction.
For the lumped load, CL dVout/dt=Ip−In and EC=CL Vout²/2. Instantaneous VDD Ip equals nMOS heat power plus pMOS heat power plus dEC/dt. Zero net capacitor current can coexist with nonzero through-current and heat.
The model solves one input step, linear ramp or exact-balance hold over 50 ns. It integrates output voltage, both heats, supply energy and supplied charge. Waveform corners are respected, rail violations are reported rather than concealed, and inspecting a time reads the same solved experiment.
Output 50% elapsed time is measured from the start of the input edge. Propagation delay here subtracts the input’s own 50% time. For a finite ramp these numbers differ. If a record does not reach the threshold, no crossing time is invented.
At the same voltage, a new capacitance changes stored charge and energy. Therefore changing CL resets the transient and its ledger. For matched abrupt steps, doubling CL doubles this model’s delay and completed cycle energy.
Charging a 10 pF output from 0 to 5 V draws 250 pJ, stores 125 pJ and dissipates 125 pJ in pMOS. Discharge dissipates the stored energy in nMOS. At one million complete charge/discharge cycles per second this contribution is 0.25 mW; it is not total chip power.
A separate ideal 10 kΩ–100 pF gate RC example has a 1 μs time constant. Gate-wire current charges an insulated electrode, while ideal DC oxide conduction is absent. Input-driver energy and gate-network capacitances are not included in the output-node experiment.
Threshold identifies a test current and bias. It does not promise the on-resistance measured at a different gate voltage and current. Ciss is bias-dependent measured input capacitance, not a universal output load. Real leakage also differs from the model’s ideal zero endpoint currents.
The inverter connects a semiconductor mechanism with an abstract logic reversal. The endpoint truth table is useful, but the charge and timing views explain what that abstraction leaves out.
A larger load changes both delay and stored energy. A slower input ramp can add overlap conduction. These controlled toy comparisons prepare learners to ask the right questions about a real timing or power specification.
Start with the named device, revision, quantity, units and test conditions. Keep minimum, typical and maximum values distinct, and do not transfer a convenient number to a different physical structure.
Draw supply, ground, input and output. Place pMOS, nMOS and output-capacitor cards. Label body ties separately and put an insulator card between each gate and channel.
Use (VGS,VDS) pairs (3,0), (3,0.2) and (3,2) V. Match them to 0, 0.38 and 2 mA. Explain why a channel can exist without net current.
Input low: trace supply through pMOS to the output. Input high: trace output through nMOS to ground. Never move an output-energy card through gate oxide.
For 10 pF from 0 to 5 V, assign 50 pC transferred charge. Divide 250 pJ supplied energy into 125 pJ stored and 125 pJ pMOS heat. On discharge move the stored amount to nMOS heat.
At Vin=2.5 V choose an output between 1.5 and 3.5 V. Both branches are 1.125 mA. A 20 ns hold delivers 112.5 pJ as heat while stored energy stays fixed.
Replace the load with 20 pF. Recalculate charge and energy and predict twice the abrupt-step delay. Circle the conditions in the named-device threshold/resistance comparison.
Can the output stay unchanged while the circuit still uses energy?
Paper represents stated quantities and topology; moving cards does not measure charge flow or semiconductor behavior. No powered components, disassembly or soldering are needed.
No, the gate controls a separate channel The gate is insulated. Output energy comes from the supply and channel paths; gate-wire charging is a distinct process.
0 mA at its threshold VGS is 1 V, not 3 V. At the selected threshold the strong-inversion model gives zero; real subthreshold leakage is omitted.
An inversion channel and zero net DC current Gate bias can support inversion while no drain–source voltage difference drives a net current.
Finite current independent of further VDS Pinch-off does not stop current. The flat saturation law is a bounded long-channel idealization.
pMOS from VDD pMOS has VSG=5 V and supports the supply-to-output path. Gate insulation does not prevent source/drain channel current.
Output stays fixed while heat is produced Equal branch currents cancel in the capacitor account, not in the supply. Power is 5×1.125=5.625 mW.
No, the test conditions and guarantee type differ Threshold and on-resistance are different measurements. Read the bias, current and typical/maximum columns.
Both delay and completed cycle energy double The same current law must move twice the charge. The new experiment also begins with its own initial energy; finite-ramp comparisons keep their own conditions.
MIT 6.012 Lecture 11, MOSFET current derivation and gradual-channel assumptions. Product geometry is original; lecture figures are not redistributed.
MIT 6.012 · MOSFET current modelMIT 6.012 Lecture 14, circuit/transfer characteristic and slides 20–24. Toy timing values are independently computed, not commercial specifications.
MIT 6.012 · CMOS inverterAuthor-hosted CMOS VLSI Design chapter 1, section 1.5, Figure 1.34 page 20. Used as a topology reference; no book artwork copied.
Weste and Harris · CMOS VLSI DesignTI SLUA618A, sections 2.4–2.7. Real power-switch driving differs from this ideal output-capacitance experiment.
Texas Instruments · Gate driver fundamentals2N7002 Rev. 7, Table 7, page 5. N-channel trench MOSFET, not the modeled planar device. No datasheet figures redistributed.
Nexperia · 2N7002 datasheetNIST image record labels the visual an illustration. Original 1429×883 source retains its full defect-trapping annotation and exact hash.
NIST · MOSFET illustrationNIST research account published 7 November 2017, updated 17 March 2025. This effect is an explicitly omitted-physics comparison.
NIST · Captured electrons and flash memoryNIST permits copying and distributing site information except marked copyrighted material and requests attribution. No image-specific third-party mark was found. This is not an invented CC0 license.
NIST · Copyrights and disclaimersIndependent subject review is pending.
Read the sources and model assumptions
Interactive explorationFlip real input bits on a little calculator. Build a result from simple rules, and follow a carry as it crosses four columns.
Close a switch. Follow a complete path. Give current a second route and discover what changes.
Interactive explorationConnect a realistic module to a virtual load, look inside a silicon cell, and build a day’s energy from changing light and time.