Follow one instruction.: sources & model

Write a tiny real assembly program, watch values move through a processor’s logical parts, and stop at the instant an answer becomes stored state.

What supports the explanation?

What this model assumes

1. Eight RV32I operations only; no compressed, multiplication, floating-point, atomic or privileged instructions.
2. Original serial teaching phases, not measured hardware timing, a pipeline model or a real chip floor plan.
3. No operating system, ABI, interrupts, cache, virtual memory, speculative execution, multicore traffic, I/O or energy model.
4. The protected 1 KiB memory map, loaded-program completion boundary and 1000-instruction budget are explicit host choices.
5. Reverse inspection restores immutable recorded snapshots. It does not claim reversible physical execution.
6. Editor programs are limited to 64 instructions and 6000 characters; only decimal instruction immediates, x-registers, labels and comments are accepted.
7. The real silicon photograph is separately credited. Its dimensions and architecture do not calibrate the logical blocks.
8. Reference traces and differential tests support implementation checks; architecture review, learner trials and device/export inspection remain release gates.
9. A real, deliberately small instruction subset: The eight supported operations are ADDI, ADD, SUB, LW, SW, BEQ, BNE and JAL from RV32I version 2.1. This is not the complete instruction set, a certified implementation or a simulator of a named commercial processor.
10. Finite-width arithmetic: Each register holds 32 bits. ADD and SUB keep the low 32 result bits; these instructions do not generate an arithmetic-overflow trap. 0x80000000 is 2147483648 unsigned and −2147483648 signed. Changing the display does not change the stored bits.
11. The zero register still has rules: Reading x0 gives zero; a successful write discards its result. LW into x0 still performs its memory access and can fault. It is not safe to erase an access just because its destination is x0.
12. Formats assign meaning to bit positions: Opcode and function fields select operations. Register selectors name architectural registers. SW and branch instructions do not encode a destination-register field: some positions used for rd in other formats instead carry immediate pieces.
13. Bytes, words and ordering: A word occupies four byte addresses. Storing 0x12345678 at address 260 writes hex bytes 78, 56, 34, 12 at 260, 261, 262, 263. The bit viewer’s left-to-right order does not reverse these memory bytes.
14. An explicit execution environment: Our 1 KiB teaching map reserves byte addresses 0–255 for code and 256–1023 for data. Only loaded instructions are executable. LW/SW require aligned four-byte data words beginning at 256 through 1020. These map/protection choices are our environment, not a universal RISC-V memory map.
15. Address calculation and access are separate: The ALU adds the old base register and sign-extended offset with 32-bit wrapping. The environment then checks alignment and accessibility. An address is not silently replaced by the word stored there.
16. Taken-target alignment: This subset has only four-byte instructions. A taken branch or jump to a non-four-byte-aligned target faults at that instruction before its changes commit. An untaken conditional branch does not fault for that unused target. An aligned jump outside loaded code commits, then the next fetch faults.
17. A branch is relative to the old PC: At PC 20, BNE x1,x0,−8 chooses PC 12 when x1 differs from zero, or PC 24 when it matches. The offset is in bytes; it is neither a line number nor an absolute destination.
18. Different reasons to stop: Reaching the end of loaded code is a host completion boundary, not an encoded HALT. Unsupported words and invalid accesses produce recorded faults. An infinite JAL x0,0 stops after 1000 retired instructions because of a host budget; it has not completed.
19. Teaching actions are not clock cycles: Fetch, Decode/read, Calculate, Memory and Commit are five original serial visualization phases. Real designs may overlap work and stall for memory. The sum-of-five example’s 95 teaching actions do not establish real latency, throughput, clock cycles, energy or nanoseconds.
20. Assembly and machine code: The editor resolves labels to signed byte offsets and encodes actual instruction words. It supports no host-language evaluation, pseudo-instructions or directives. Source normalization preserves instruction semantics, while snapshots preserve the selected recorded phase.
21. A photograph is physical context: The licensed CH32V003 photograph shows actual silicon from a different implementation. Repeated structures and bonding pads are visible; unverified regions are not labeled as our ALU or register file. The logical diagram and the die photograph answer different questions.

What has been checked

Analytical reference cases, conservation or transition invariants, finite drawing commands, bounded setup parsing, discovery and route integrity are checked automatically. These checks do not establish anatomical fidelity, learner outcomes or browser/device compatibility. Independent subject review, learner trials, comprehensive accessibility review and browser video encoding checks remain pending.

Each source supports the associated claim. Sources do not certify this implementation or its visuals.

About the cover illustration

Original rendering of the lesson’s logical processor blocks. Active connections reflect a recorded teaching phase, not a physical chip floor plan. The licensed Zeptobars silicon photograph is credited separately inside the lesson.