How does a CPU turn instructions into results?

Fetch the right card

The program counter, or PC, is a byte address. It selects four loaded instruction bytes. The instruction register holds the word assembled from them.

Read the job and its operands

The decoder reads the instruction’s fields. An ADD chooses two register values; an immediate instruction also contains a signed constant. A destination that is also a source is read before its replacement is committed.

Calculate, then wait

An arithmetic logic unit, or ALU, computes a result or an effective memory address. At the 7 + 5 checkpoint, the pending result is 12 but x3 is still 0.

Use memory only when requested

LW loads a four-byte word from its computed address. SW prepares four bytes for a store. An arithmetic-only instruction has no data-memory access in its Memory phase.

Commit the change

Our serial teaching machine updates architectural registers or data memory, the PC and the retired-instruction count together. You can restore an earlier recorded snapshot; this does not make a real processor run backward.

Choose the next instruction

Ordinary instructions advance by four bytes. A taken branch adds its signed offset to the executing instruction’s PC. JAL also saves PC + 4 in its chosen destination, unless that destination is x0.

Try an unseen program

Change 7 and 5 to 9 and 4 and predict 13. Replace ADD with SUB and predict 5. Then run the guarded sum loop at N = 3: its stored result is 6 after 13 retired instructions.

A real, deliberately small instruction subset

The eight supported operations are ADDI, ADD, SUB, LW, SW, BEQ, BNE and JAL from RV32I version 2.1. This is not the complete instruction set, a certified implementation or a simulator of a named commercial processor.

Finite-width arithmetic

Each register holds 32 bits. ADD and SUB keep the low 32 result bits; these instructions do not generate an arithmetic-overflow trap. 0x80000000 is 2147483648 unsigned and −2147483648 signed. Changing the display does not change the stored bits.

The zero register still has rules

Reading x0 gives zero; a successful write discards its result. LW into x0 still performs its memory access and can fault. It is not safe to erase an access just because its destination is x0.

Formats assign meaning to bit positions

Opcode and function fields select operations. Register selectors name architectural registers. SW and branch instructions do not encode a destination-register field: some positions used for rd in other formats instead carry immediate pieces.

Bytes, words and ordering

A word occupies four byte addresses. Storing 0x12345678 at address 260 writes hex bytes 78, 56, 34, 12 at 260, 261, 262, 263. The bit viewer’s left-to-right order does not reverse these memory bytes.

An explicit execution environment

Our 1 KiB teaching map reserves byte addresses 0–255 for code and 256–1023 for data. Only loaded instructions are executable. LW/SW require aligned four-byte data words beginning at 256 through 1020. These map/protection choices are our environment, not a universal RISC-V memory map.

Address calculation and access are separate

The ALU adds the old base register and sign-extended offset with 32-bit wrapping. The environment then checks alignment and accessibility. An address is not silently replaced by the word stored there.

Taken-target alignment

This subset has only four-byte instructions. A taken branch or jump to a non-four-byte-aligned target faults at that instruction before its changes commit. An untaken conditional branch does not fault for that unused target. An aligned jump outside loaded code commits, then the next fetch faults.

A branch is relative to the old PC

At PC 20, BNE x1,x0,−8 chooses PC 12 when x1 differs from zero, or PC 24 when it matches. The offset is in bytes; it is neither a line number nor an absolute destination.

Different reasons to stop

Reaching the end of loaded code is a host completion boundary, not an encoded HALT. Unsupported words and invalid accesses produce recorded faults. An infinite JAL x0,0 stops after 1000 retired instructions because of a host budget; it has not completed.

Teaching actions are not clock cycles

Fetch, Decode/read, Calculate, Memory and Commit are five original serial visualization phases. Real designs may overlap work and stall for memory. The sum-of-five example’s 95 teaching actions do not establish real latency, throughput, clock cycles, energy or nanoseconds.

Assembly and machine code

The editor resolves labels to signed byte offsets and encodes actual instruction words. It supports no host-language evaluation, pseudo-instructions or directives. Source normalization preserves instruction semantics, while snapshots preserve the selected recorded phase.

A photograph is physical context

The licensed CH32V003 photograph shows actual silicon from a different implementation. Repeated structures and bonding pads are visible; unverified regions are not labeled as our ALU or register file. The logical diagram and the die photograph answer different questions.

Debugging a wrong answer

Find the first incorrect state transition: operand read, operation, address, store bytes or branch target. Compare the full trace with a prediction instead of looking only at the final number.

Reading a performance claim

Ask whether the quantity is instructions, cycles, elapsed time or throughput, and which processor and memory conditions were measured. This model exposes behavior but supplies no real-chip timing evidence.

From transistors to programs

Transistor circuits can implement logic and storage; an instruction-set contract organizes their visible effects. The next level does not erase the physical constraints of the previous one.

Which selects the operation at PC 8: the IR word, the address 8 or operand 7?

• The address 8
• The IR word’s fields
• Operand 7

ALU preview 12, x3 still 0: has this ADD committed?

• Yes
• No
• Only in signed display

LW x1,256(x0), with word256=0x12345678, returns…

• 256
• 0x12345678
• The instruction address

Store 0x12345678 at 260. What are bytes 260–263 in hex?

• 12 34 56 78
• 78 56 34 12
• 26 00 00 00

At PC 20, BNE x1,x0,−8 with x1=4 selects…

• PC −8
• PC 12
• PC 24

0x7fffffff + 1 produces which signed display?

• 2147483648 with a wider register
• −2147483648
• An arithmetic-overflow trap

Is LW x0,258(x0) a harmless no-op here?

• Yes, x0 discards everything
• No, the misaligned access faults
• Only if memory contains zero

Do 95 teaching phases prove 95 real CPU cycles?

• Yes
• No
• Only at 1× playback

Architectural effects and encodings of the selected operations

Versioned RV32I 2.1: integer registers, arithmetic, control transfers, loads/stores and x0. The restricted teaching environment and phase schedule are separately authored.

Independent published encoding examples

LLVM 17.0.6 assembler test vectors provide byte-level examples for all eight supported mnemonics. They test encoding, not whether a runtime address is valid.

Independent non-faulting architectural comparison

Pinned mini-rv32ima core compared against PC, all registers and memory bytes. Its environment differs; it is not the lesson fault authority or a conformance certificate.

A real implementation has its own pipeline and stalls

Ibex implementation documentation distinguishes instruction behavior from pipeline details. Our five serial phases are not an Ibex timing diagram.

Actual silicon photograph and measured sample dimensions

Mikhail Svarichevsky, 1 February 2024: CH32V003 J4M6 sample, 1732×1172 μm die. No speculative process-node estimate is adopted.

Photograph reuse rights

Zeptobars copyright notes license die shots under CC BY 3.0 and request a source link. Original bytes are retained with visible author/source/license credit.